In traditional designs of receiver circuitry, the receiver circuitry is configured to operate from a supply voltage that matches the “native voltage” (also referred to as a “technology limit value”) of the components within the receiver circuitry. The voltage drop across any terminals of the components that make up the receiver circuitry should be lower than the native voltage in order to prevent damage due to overstress, which may in turn lead to reduced reliability. For example, if the receiver circuitry is constructed from CMOS devices with a native voltage of 1.8V, the receiver circuitry will typically utilise a 1.8V supply voltage. This supply voltage may well exceed the supply voltage of the destination voltage domain (for example in one example implementation the destination voltage domain may operate from a supply voltage of around 1V), and the receiver circuitry will generate an output signal that is down converted to the supply voltage range of the destination voltage domain.
The above approach works well provided that the voltage of the input signal does not vary in a range that exceeds the supply voltage of the receiver circuitry, i.e. in the above example the input signal does not vary in a range greater than 0 to 1.8V. However, in modern systems there is an increasing requirement for the receiver circuitry to be able to receive an input signal from a source voltage domain whose supply voltage may exceed the native voltage of the components used by the receiver circuitry. Considering the above specific case, it may for example be desirable for the receiver circuitry to also be able to handle input signals from a 2.5V or 3.3V source voltage domain. However, wherever the source voltage domain operates from a supply voltage that exceeds the native voltage of the components within the receiver circuitry, this can give rise to reliability problems due to components within the receiver circuitry potentially being exposed to a voltage overstress during the course of operation.
In addition, it is often desirable for the same design of receiver circuitry to be used in a range of different scenarios where the supply voltage of the source voltage domain may differ. For example, it would be useful for the same receiver circuitry to be able to operate with input signals that have a variety of different ranges of voltage swing, for instance 0 to 1.8V, 0 to 2.5V or 0 to 3.3V using the earlier examples. Indeed, in certain instances the source voltage domain may be able to switch between multiple different supply voltages (for example in different operating modes), and accordingly the receiver circuitry needs to be able to operate correctly irrespective of the current source supply voltage used by the source voltage domain.
However, in addition to the earlier mentioned overstress problem that can occur when the receiver circuitry is exposed to a source voltage domain whose supply voltage exceeds the native voltage of the components used by the receiver circuitry, another problem that can arise is in reliably detecting logic low to logic high and logic high to logic low transitions in the input signal across the various different voltage ranges of the input signal, in situations where the receiver circuitry operates from a supply voltage matching the native voltage of its components.
In particular, if the minimum input voltage that will cause detection of a logic high state of the input signal is referred to as VIH, and the maximum input voltage that will cause detection of a logic low state of the input signal is referred to as VIL, a situation can arise where there is insufficient margin to reliably detect the logic high and logic low states. For example, consider an instance where the input connection of the receiver circuitry is connected to a 3.3V driver in the system. In this instance, JEDEC TTL levels indicate that if the receiver circuitry uses a 1.8V supply voltage, then its corresponding VIH and VIL values would be 2V and 0.8V respectively. Hence such a receiver circuit would have to be sized to have its trip point for detecting a logic low level set higher than 0.8 V and its trip point for detecting a logic high level set lower than 2V. If the same receiver circuitry was then used to detect an input signal using a 1.8V supply voltage, then its VIH and VIL values would be 1.155V and 0.585V, respectively. The trip points would hence have to be set having regards to the lowest VIH and highest VIL, and in the above example it will be seen that there will hence only be a margin of 0.355V between the lowest VIH and highest VIL values. It is difficult to maintain reliable trip points with such a small margin across all process corners. Moreover, if effects such as noise are introduced, then this will further reduce the margin, potentially causing incorrect operation.
Accordingly, it would be desirable to provide an improved receiver circuitry design that alleviates the above-mentioned issues.